1. Field of the Invention
The present invention relates to a delay circuit and a video signal processing circuit using the delay circuit.
2. Description of the Related Art
Analog color television systems which are employed in the world are broadly divided into three systems, i.e., NTSC (National Television Standards Committee) system employed mainly in Japan and North/Central America, PAL (Phase Alternation by Line) system employed mainly in the West European countries, and SECAM (SEquential Couleur A Memoire) system employed mainly in the East European countries. The NTSC system is a system of an interlaced scanning of 30 frames/sec, each frame having 525 horizontal scanning lines, with a horizontal scanning frequency at 15.75 kHz and with a vertical scanning frequency at 60 Hz. The PAL system is a system of an interlaced scanning of 25 frames/sec, each frame having 625 horizontal scanning lines, each of which is phase-inverted. The SECAM system is a system of an interlaced scanning of 25 frames/sec, each frame having 625 horizontal scanning lines. In this manner, all the systems of the NTSC, PAL, and SECAM basically perform the interlaced scanning and, as shown in FIG. 10, transmit one screen by two separate scan of one frame for an odd-numbered field and for an even-numbered field. The one frame consists of the odd-numbered field and the even-numbered field. More specifically, in the interlaced scanning, all the scanning lines in the odd-numbered field are scanned every alternate scanning line from top to bottom of the screen. The scanning of the last scanning line in the odd-numbered field is then discontinued halfway and all the scanning lines in the even-numbered field are scanned from top to bottom as if the interstices of all the scanning lines in the odd-numbered field are filled up.
In the NTSC, PAL, and SECAM systems, video signals of R (red), G (green), and B (blue) captured as an image by a television camera are not transmitted in their original forms, but there is employed a scheme of converting the video signals captured as an image into a luminance signal Y representing brightness of the screen and a chroma signal C representing the level of shading of the screen color, and further of transmitting a composite signal SC which is obtained by compositing the luminance signal Y and the chroma signal C. FIG. 11 shows examples of waveforms of a chroma signal C, a luminance signal Y, and a composite signal SC. The chroma signal C shown in (A) of FIG. 11 is a signal obtained by converting two color-difference signals R-Y and B-Y that are obtained by subtracting the luminance signal Y from the R signal and B signal, respectively, into mutually orthogonal I•Q signal (case of NTSC system) or U•V signal (case of PAL system) and by compositing and amplitude modulating the signals. The chroma signal C includes a color burst signal BS and a carrier chrominance signal CA. Note that the color burst signal BS is a signal to be used as a reference of the phase and amplitude of the carrier chrominance signal CA, and that the carrier chrominance signal CA is a signal with a phase thereof indicative of a hue with an amplitude thereof indicative of chroma. The luminance signal Y shown in (B) of FIG. 11 includes a horizontal synchronizing signal HSYNC and a luminance signal YA. Note that the horizontal synchronizing signal HSYNC is a signal indicative of the start of a single scanning line in the horizontal direction, and that the period between the two adjacent horizontal synchronizing signals HSYNC is called “1H period (one horizontal scanning period: about 64 μsec)”. The luminance signal YA is a signal indicative of the details of the luminance. The composite signal SC shown in (C) of FIG. 11 is a composite of the chroma signal C shown in (A) of FIG. 11 and the luminance signal Y shown in (B) of FIG. 11. More specifically, the composite signal SC has a waveform obtained by superimposing the color burst signal BS of the chroma signal C on the back porch of the luminance signal Y and by superimposing the carrier chrominance signal CA of the chroma signal C on the luminance signal YA.
By the way, the overseas PAL and SECAM systems require the video signal processing circuit on the receiving side to delay color-difference signals R-Y and B-Y demodulated from video signals received at the antenna by 1H period and to combine the 1H-period delayed signals with the most recent color-difference signals R-Y and B-Y, to thereby eliminate distortions arising on transmission paths and to thereby match the color-difference information of all the scanning lines by line correction. The mainstream of such a circuit for delaying by 1H period (hereinafter, referred to as a 1H-delay circuit) has hitherto been of a type using CCD (Charged Coupled Device) delay element (see, e.g., Japanese Patent Application Laid-Open Publication No. 1997-191472).
However, although the video signal processing circuit except the CCD delay element for 1H-delay circuit has hitherto been designed and manufactured exclusively by a bipolar process capable of handling analog signals easily, a shift to the next-generation BiCMOS process capable of handling both the bipolar and CMOS would enable the video signal processing circuit inclusive of the CCD delay element to be made into one chip for low-cost designing and manufacturing. It is also proposed to use as the 1H-delay circuit instead of the CCD delay element a “switched capacitor circuit” that is more inexpensive than the CCD delay element and that has hitherto been used dedicatedly as an analog filter.
FIG. 12 shows an example of a conventional configuration of the delay circuit using the switched capacitor circuit. Note that although the delay circuit shown in FIG. 12 includes two switched capacitor units for simplification of explanation, the number of the switched capacitor units may vary depending on the delay time required.
NMOS transistors M1 and M2 have their respective source electrodes that are connected in common to a capacitive element C1 to make up a single switched capacitor unit 10a. Similarly, NMOS transistors M3 and M4 have their respective source electrodes that are connected in common to a capacitive element C2 to make up a single switched capacitor unit 10b. Note that an input voltage VIN to be delayed is applied to drain electrodes of the NMOS transistors M1 and M3, while the drain electrodes of the NMOS transistors M2 and M4 are connected to a non-inverting input terminal of a voltage follower 12. A switching control circuit 11 is disposed to control on/off switching operations of the NMOS transistors M1 to M4. Note that the switching control circuit 11 inputs a switch signal SW1 to a gate electrode of the NMOS transistor M1, inputs switch signals SW2 to gate electrodes of the NMOS transistors M2 and M3, and inputs a switch signal SW3 to a gate electrode of the NMOS transistor M4. Such a configuration allows the voltage follower 12 to output an output voltage VOUT that is delayed from the input voltage VIN by a period of switching cycle of the NMOS transistors M1 to M4.
FIG. 13 is timing chart showing operation examples of the delay circuit shown in FIG. 12. Note that the level of the input voltage VIN is assumed to shift from D0 to D4 in respective periods segmented by times T0 to T5 (see (A) of FIG. 13), and that respective periods segmented by times T0 to T5 are correlated with the period of switching cycle of the NMOS transistors M1 to M4.
First, at time T0, the switching signals SW1 to SW3 input to the gate electrodes of the NMOS transistors M1 to M4 go at low, high, and low, respectively, and keep those states till time T1 (see (B) to (D) of FIG. 13). That is, at time T0, the NMOS transistors M1 and M4 are turned off and the NMOS transistors M2 and M3 are turned on, being kept in those states till time T1 (see (E) to (G) of FIG. 13). Thus, there is formed a charging path of the NMOS transistor M3 and the capacitive element C2 in the period of time T0 to T1, with the result that electric charge corresponding to the level D0 of the input voltage VIN in such a period is charged into the capacitive element C2 via the NMOS transistor M3, to thereby cause information on the level D0 of the input voltage VIN to be held (see (I) of FIG. 13). On the other hand, there is formed a discharging path of the NMOS transistor M2 and the capacitive element C1, while any electric charge is not yet held on the capacitive element C1 (see (H) of FIG. 13) with the output voltage VOUT remaining uncertain (see (J) of FIG. 13).
Next, at time T1, the switch signals SW1 to SW3 input to the gate electrodes of the NMOS transistors M1 to M4 go at high, low, and high, respectively, and keep those states till time T2 (see (B) to (D) of FIG. 11). That is, at time T1, the NMOS transistors M1 and M4 are turned on and the NMOS transistors M2 and M3 are turned off, being kept in those states till time T2 (see (E) to (G) of FIG. 11). Thus, there is formed a charging path of the NMOS transistor M1 and the capacitive element C1 in the period of time T1 to T2, with the result that electric charge corresponding to the level D1 of the input voltage VIN in such a period is charged into the capacitive element C1 via the NMOS transistor M1, to thereby cause information on the level D1 of the input voltage VIN to be held (see (H) of FIG. 13). On the other hand, there is formed a discharging path of the NMOS transistor M4 and the capacitive element C2, with the result that electric charge held on the capacitive element C2 is discharged to thereby cause the input voltage VIN of the level D0 corresponding to the electric charge to be read out (see (I) of FIG. 13) and to be applied to the non-inverting input terminal of the voltage follower 12. This allows the voltage follower 12 to output the output voltage VOUT that is delayed from the input voltage VIN of the level D0 by the period of switching cycle of the NMOS transistors M1 to M4 (see (J) of FIG. 13). Then, afterward, the above operation is repeated in each of periods of time T2 to T3, time T3 to T4, time T4 to T5.
By the way, the switched capacitor circuit has hitherto been used exclusively as the analog filter. In the case of the analog filter use, employed as a cut-off frequency that is one of the filter characteristics is a much lower frequency than the frequency of the operation clock (switching signal) of the switched capacitor circuit for use in the delay circuit as shown in FIG. 12. For example, when the switched capacitor circuit is used to delay 1H period the color-difference signals R-Y and B-Y in the field of video signal processing, the frequency is of the order of several megahertz (MHz), whereas in the case of the analog filter use, the frequency is mainly of the order of several hundred hertz (Hz) to several kilohertz (kHz). Accordingly, the following problems may occur in the case of using the switched capacitor circuit as the delay circuit.
Describing based on the delay circuit of FIG. 12, rise and fall of the output voltage responding to the input voltage undergo effects of difference of slew rate depending on the difference in the input/output voltage characteristics of the NMOS transistors M1 to M4 in the switched capacitor units 10a and 10b. The NMOS transistors M1 to M4 have their respective thresholds of input voltage defined as branch points of whether the logical levels of the respective output voltages become at high or low. The slew rate and the threshold of the input voltage may have their respective manufacturing dispersions for each of the NMOS transistors M1 to M4 and further may vary depending on the ambient temperatures or loads.
Thus, irrespective of the switching signals SW1 to SW3 input from the switching control circuit 11 to the gate electrodes of the NMOS transistors M1 to M4 to turn on/off the NMOS transistors M1 to M4 at the same time (see (A) to (C) of FIG. 14), the respective input/output rise and fall periods of the NMOS transistors M1 to M4 may have non-negligible lengths as compared with one cycle of the operation clock in the delay circuit use and may also have dispersions, resulting in the states where all the NMOS transistors M1 to M4 are turned on (the hatched portions of (D) to (F) of FIG. 14).
Although originally the NMOS transistors M1 and M4 are to switch from off to on and the NMOS transistors M2 and M3 are to switch from on to off instantly at time T1 shown in (A) to (J) of FIG. 13, any period may occur in which all the NMOS transistors are turned on as shown in (A) to (F) of FIG. 14. In this case, though the NMOS transistor M3 should originally be turned off at time T1 to cut off the charging path to the capacitive element C2 so that electric charges held on the capacitive element C2 in the preceding period of T0 to T1 are preserved, there will be formed a charging path of the NMOS transistor M3 and the capacitive element C2. As a result, electric charges corresponding to the level D1 of the input voltage VIN are charged not only into the capacitive element C1 via the NMOS transistor M1 but also into the capacitive element C2 via the NMOS transistor M3. This may also result in formation of an abnormal closed loop extending from the capacitive element C1 through the NMOS transistors M2 and M4 to the capacitive element C2.
In this manner, when using the switched capacitor circuit as the delay circuit, such a case may possibly occur that all the switching elements of the switched capacitor circuit are turned on at the same time, whereupon the switched capacitor circuit may not effect its normal operations expected as the 1H-delay circuit.